1. Field of the Invention
The present invention generally relates to a liquid crystal display device, and particularly to a thin-film transistor used in a liquid crystal display device and the like.
2. Description of Related Art
The liquid crystal display device is widely used as a display device of a portable (or lap-top) information processing apparatus. Recently, attempts to use the liquid crystal display device as a high-resolution color display device of a stationary (or desk-top) information processing apparatus have started.
Among several types of liquid crystal display devices, the active matrix liquid crystal display device, in which an individual pixel is driven by a thin-film transistor (TFT), is suitable for attaining the above-mentioned high-resolution color display. The active matrix driving method can eliminate crosstalk between pixels which may occur in the passive matrix driving method, and hence can provide superior display performance. In the active matrix driving method, TFTs are arranged on one of the glass substrates that constitute a liquid crystal panel and each TFT controls a voltage applied to a corresponding, transparent pixel electrode.
In the active matrix liquid crystal display device, TFTs are formed on a glass substrate, and therefore an amorphous silicon pattern or a polycrystal silicon (i.e., polysilicon) pattern is used as an active layer such as a channel layer, which is in contrast to the case of a usual transistor formed on a single crystal silicon substrate. Although polysilicon has a higher carrier mobility than amorphous silicon and hence is suitable for a TFT, it substantially has a higher defect density than single crystal silicon because it includes grain boundaries etc. in the crystal structure. As a result, a polysilicon TFT tends to have a large leak current.
To minimize such leak current, in many cases the LDD (lightly doped drain) structure is used in TFTs of a liquid crystal display device. In the LDD structure, a portion of a drain region adjacent to a channel region is given a somewhat lower impurity concentration and the degree of electric field concentration on the channel region is reduced by allowing an electric field to develop in the above portion.
To further reduce the leak current, the polysilicon TFT is provided with the multi-channel gate structure in which two TFTs are connected together in series.
FIG. 3 shows an example of a conventional multi-channel gate TFT, which is a simplified version of a TFT proposed in Y. Matsueda, M. Ashizawa, S. Aruga, H. Ohshima, and S. Morozumi, "New Technologies for Compact TFT LCDs with High-Aperture Ratio, SID 90 Digest, pp. 315-318.
Referring to FIG. 3, the TFT includes a polysilicon pattern 11 formed on a glass substrate 10 that constitutes a liquid crystal panel, and a gate bus pattern 12 formed above the polysilicon pattern 11. The gate bus pattern 12 is formed with branches 12A and 12B that cover the polysilicon pattern 11. The polysilicon pattern 11 constitutes an active portion of the TFT and doped with an n-type or p-type impurity excluding the portions covered with the branches 12A and 12B. That is, in the polysilicon pattern 11, first and second channel regions are formed so as to correspond to the portions covered with the branches 12A and 12B, respectively, and diffusion regions serving as source and drain regions are formed on both sides of each channel region.
The gate bus pattern 12 is made of Al or Al alloy each of which has low resistivity. The TFT further includes a data bus pattern 13 that is formed in a level higher than the gate bus pattern 12 and is also made of Al or Al alloy. One end of the polysilicon pattern 11 is connected to the data bus pattern 13 at through contact hole 11a. The other end of the polysilicon pattern 11 is connected to a transparent pixel electrode 14 through a contact hole 11b.
In the TFT having the above configuration, a drive voltage that is supplied via the data bus pattern 13 is applied to the transparent pixel electrode 14 under the control of a gate voltage that is supplied via the gate bus pattern 12, thereby causing a variation in the orientation of corresponding liquid crystal molecules. Since the first and second channel regions that correspond to the branches 12A and 12B are formed in series, the leak current during an off-state of the transistor is very small, allowing high-contrast display. The leak current can further be reduced by forming LDD regions as mentioned above immediately outside the first and second channel regions.
However, the following problems occur in forming LDD regions in the multi-channel gate TFT concerned. That is, since the gate bus pattern 12 has a complex shape including the branches 12A and 12B, ion implantation to form diffusion regions in the polysilicon pattern 11 likely becomes non-uniform. For example, in the case of the FIG. 3 structure, if ions are implanted into the polysilicon pattern 11 by using the gate bus pattern 12 as a mask, a shadow occurs in a region between the branches 12A and 12B and the impurity concentration tends to be lower there.
In the multi-channel gate TFT in which the gate bus pattern 12 has the branches 12A and 12B, a mask is used in an ion implantation step for forming LDD structures. If a mask alignment error occurs in this ion implantation step, resulting LDD regions on the right and left sides of each gate will have different lengths.
FIGS. 4A to 4C illustrate the problem caused by a mask alignment error in the ion implantation step. FIG. 4A is a plan view showing the main part of the FIG. 3 structure, FIG. 4B is a sectional view showing formation of LDD regions in the polysilicon pattern 11 in the FIG. 4A structure in the ideal case where no mask alignment error occurs, and FIG. 4C is a sectional view showing formation of LDD regions in a case where a mask alignment error occurs.
Referring to FIG. 4A, a step of forming LDD regions in the polysilicon pattern 11 by ion implantation will be described below. After masks 15A and 15B that are a little wider than the branches 12A and 12B are formed on the branches 12A and 12B, p-type or n-type ions are implanted through the masks ISA and 15B at a given dose, so that diffusion regions 11A to 11C to become source and drain regions of the TFT are formed in the polysilicon pattern 11 as shown in the sectional view of FIG. 4B. After the masks 15A and 15B are removed, ion implantation is performed at a lower dose, so that LDD regions 11D to 11G on both sides of the branches 12A and 12B of the gate bus pattern 12. FIGS. 4B and 4C are sectional views taken along line A-A' in FIG. 4A.
As seen from FIG. 4B, an oxide film 11a is formed on the polysilicon pattern 11 and the branches 12A and 12B of the gate bus pattern 12 are formed on the oxide film 11a. It is also seen that a first channel region CH.sub.1 and a second channel region CH.sub.2 are formed in the polysilicon pattern 11 right under the branches 12A and 12B, respectively.
As shown in FIG. 4B, where the masks 15A and 15B are ideally aligned with the branches 12A and 12B and hence with the channel regions CH.sub.1 and CH.sub.2 formed thereunder, the LDD regions 11D to 11G have a given length L.sub.DD. However, as shown in FIG. 4C, where the masks 15A and 15B are deviated from the channel regions CH.sub.1 and CH.sub.2, the LDD regions 11D and 11F located on the left side of the branches 12A and 12B, respectively, have an increased length L.sub.DD +d while the LDD regions 11E and 11G on the opposite side have a decreased length L.sub.DD -d. In other words, in the multi-channel gate TFT of FIG. 4C, the LDD regions on the right and left sides of each gate have different lengths, so that device characteristics obtained with positive and negative drain voltages become asymmetrical.
Further, in the conventional TFT shown in FIGS. 3 and 4A to 4C, the LDD regions need to be shielded from light by a light-interrupting film to prevent an increase in leak current. Therefore, in the TFT under consideration, a light-interrupting mask for shielding the LDD regions 11D to 11G needs to be provided separately from a conventionally provided light-interrupting mask for shielding the gate bus pattern 12. However, the provision of the additional light-interrupting mask reduces the aperture ratio, resulting in darker images displayed.